RTI FPGA Programming Blockset

Integrating FPGA models in dSPACE systems

The RTI FPGA Programming Blockset is a Simulink blockset for using a FPGA model created with a dSPACE system using the Xilinx® System Generator Blockset.

The end of life of the dSPACE PHS (peripheral high-speed) hardware for modular systems is planned for December 31, 2024. You can still buy the related products up to and including December 31, 2021. New Releases of dSPACE software will still support the dSPACE PHS hardware for modular systems until at least the end of 2023. Although the RTI FPGA Programming Blockset still supports PHS hardware, we advise against using the PHS hardware products in new projects. For new projects we recommend that you use SCALEXIO, the latest dSPACE technology for modular real-time systems.

Application Areas

The RTI FPGA Programming Blockset is a Simulink blockset for using a FPGA model created with a dSPACE system using the Xilinx® System Generator Blockset. It provides RTI blocks for implementing the interface between the FPGA mounted on a dSPACE board and its I/O, and the interface between the dSPACE FPGA board and its computation node.

The blockset can be used with the following dSPACE FPGA platforms, which provide user-programmable FPGAs:

  • DS2655 FPGA Base Board and its I/O modules.
  • DS6601/DS6602 FPGA Base Boards and their I/O modules.
  • MicroAutoBox II 1401/1511/1514 and 1401/1513/1514 extended with I/O modules.
  • MicroAutoBox III 1403/1511/1514 and 1403/1513/1514 extended with I/O modules.
  • MicroLabBox.

Typical application scenarios for rapid control prototyping (RCP) and hardware-in-the-loop (HIL) simulation are:

  • Projects in the automotives, industrial automation, medical engineering and aerospace industries
  • Signal preprocessing, adapting new interfaces, very fast control loops, designing and testing new concepts for electrified powertrains

Key Benefits

The dSPACE FPGA platforms provide a Xilinx® FPGA for which you can implement an application graphically by using Xilinx® System Generator in Simulink. The RTI FPGA Programming Blockset lets you integrate the resulting FPGA model in a Simulink model that runs on dSPACE hardware. The RTI FPGA Programming Blockset gives you a convenient way to connect the I/O board’s I/O driver components and to model the connection to a processor-based computation node (SCALEXIO processing hardware, MicroLabBox or MicroAutoBox). The data exchange supports fixed-point data types as well as floating-point data types. Thus, FPGA programming is seamlessly integrated into the Simulink environment. With the FPGA blockset, you can synthesize, build and program the FPGA or processor directly from Simulink for optimal convenience. During run time, you can access variables to trace or modify them, without having to modify the model.

Alternatively, the handcode interface lets you program the FPGA boards in VHSIC Hardware Description Language (VHDL) or Verilog. 

Functionality Description
General
  • Integrating an FPGA model on a dSPACE FPGA platform
  • I/O configuration
  • Automatic generation of a processor model template on the basis of an FPGA application
FPGA interface
  • Programming the FPGA with the Xilinx® System Generator
  • Integrating an FPGA model created with the Xilinx® System Generator
  • Offline simulation in Simulink
Handcode interface
  • Programming the FPGA in VHDL or Verilog
I/O access
  • Connecting the FPGA model with analog and digital input and output signals with the RTI FPGA Blockset
Processor-FPGA communication
  • Connecting the FPGA model with the processor model running on the computation node (SCALEXIO processing hardware, MicroLabBox or MicroAutoBox)
  • Access types for system bus communication with the dSPACE FPGA platforms: register, register groups, buffer
Inter-FPGA communication between SCALEXIO FPGA base boards
  • Via I/O Module Slots offers lowest latencies

  • Via MGT Module provide highest bandwidth

  • Via IOCNET offers highest flexibility

Asynchronous tasks
  • Implementing interrupt-driven tasks in the processor model triggered from the FPGA model
Variable access1)
  • Tracing of register values, e.g., dSPACE in ControlDesk directly without model changes
  • Changing constant values during run time of the FPGA application without modeling
Remote FPGA build
  • Support of separate PCs for performing the FPGA build so that the PC used for modeling is not blocked
  • The build process can be observed using an extra tool
 
1) Available for SCALEXIO systems, MicroAutoBox, and MicroLabBox with the RTI FPGA Programming Blockset FPGA Interface sublibrary.

  • RTI FPGA Progammable Blockset Product Information, PDF, English, 792 KB
Contact Information

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