About This Training

dSPACE offers a range of real-time components with FPGAs that can be programmed in a block-oriented environment. The AMD Vitis™ Model Composer HDL Library, previously known as Xilinx System Generator (XSG), is integrated directly into MATLAB®/Simulink®, aligning the process of modeling FPGA implementations to that of modeling microprocessors and therefore accelerating the development and testing phase.

The FPGA Basic training will provide you with the basic skills needed to successfully embed applications on dSPACE FPGA hardware. You will learn how to set up an FPGA model, exchange parameters between the processor and FPGA, check timing behavior and resource consumption, perform an FPGA build process, embed the build result in ConfigurationDesk and download/program the FPGA on the real-time system. This training uses a SCALEXIO-based platform with a DS2655 FPGA Base Board and a DS2655M1 Multi-I/O FPGA Module.

Additionally, you will receive an overview and functional description of the AMD third-party elements, which include only basic elements. The dSPACE XSG Utils Library offers more advanced functions that allow you to model your design efficiently. Tasks such as integrating look-up tables (LUT) of up to 4 dimensions or a PWM generator/measurement on the FPGA can be done with just a few clicks. You can also integrate scope functionality, which enables you to monitor FPGA signals at the FPGA clock rate (e.g., 8 ns) in ControlDesk during online simulation. All library components are implemented as open XSG-based models, and the main parameters can be tuned online. You will learn how to use these libraries and the dSPACE modeling structure in a hands-on session.

The course covers the basics required for embedding a real-time FPGA application, parameterizing plant models, monitoring current status, and accessing onboard I/O.

Course Content

• Introduction to FPGA technology.
• Building FPGA models using AMD and the dSPACE programming blockset including constraints, testing, and a debugging workflow.
• Overview of FPGA-based dSPACE solutions (XSG).
• PWM signal generation on dSPACE real-time hardware using FPGA-based Utils solution library.
• I/O scaling and signal visualization.
• FPGA model parameterization during run time using ControlDesk.
• Visualization of internal FPGA states, with time resolution equal to the FPGA clock.

Target Group​

• Developers of fastest control loop design.
• Developers of quasi-continuous plant models.
• Everyone to whom processor-based simulation is not fast enough.

Requirements

• MATLAB®/Simulink®
• ControlDesk
• ConfigurationDesk